1. Field of the Invention
The present invention relates to a semiconductor device and its wiring and a fabrication method thereof. More specifically, the present invention relates to an improved semiconductor device and its wiring and a fabrication method thereof which are implemented by serially arranging at least two films which have different materials from each other.
2. Description of the Background Art
The gate electrode of a known semiconductor device is formed in a structure where a silicide layer or a metal layer is deposited on a polysilicon layer in order to decrease resistance. The gate electrode includes wiring for transferring electrical signals therethrough. Therefore, the gate electrode represents all kinds of wiring which are used as an element of the transistor and which are used for the semiconductor device for transferring electrical signals.
Recently, a multilayer film gate electrode technique has been developed to form a polysilicon layer, a diffusion barrier layer and a metallic film when the ource and/or drain are formed via a self-alignment technique. In the multilayer film gate electrode technique, a dopant diffusion barrier layer consisting of a titanium nitride TiN is formed between a polysilicon layer and a suicide layer.
In addition, conventional devices are known to utilize a multilayer film structure of a polysilicon layer and a metal film, or a polysilicon, a diffusion barrier layer and a metal film. Also, the electrical characteristics of a gate electrode which is formed in a single layer structure of a metallic layer were reported.
The known wiring(gate electrode) of a semiconductor device and a wiring structure thereof will now be explained with reference to the accompanying drawings.
FIG. 1A illustrates the structure of a known semiconductor device. A p-type semiconductor substrate is generally used for fabricating an n-channel transistor and an n-type semiconductor substrate is used for fabricating a p-channel transistor. The semiconductor device having an n-channel transistor will now be explained
An insulation film 2 is formed on the upper surface of a semiconductor substrate 1 which is doped with a p-type impurity, a gate electrode 3 is formed on the insulation film 2 and a conductive n-type dopant layer 4 is formed at the surface of the semiconductor substrate 1 at both sides of the gate electrode 3. At this time, the insulation film 2 is generally an oxide film which is formed by a thermal oxide method. Alternatively, the insulation film 2 may be an insulator having a high dielectric constant such as a nitride film. The insulation film 2 is well known as a gate oxide film. The gate electrode 3 is formed of a multilayer film having a metal layer pattern or a silicide layer pattern 3b deposited on a doped polysilicon layer pattern 3a. Hereinafter, the metal layer and the silicide layer are referred as a metallic film. Therefore, the metallic film pattern 3bdenotes a metal layer pattern or a silicide layer pattern. As the metallic film pattern 3b which is an upper layer of the gate electrode 3, a metal layer formed of W or TiN, and a silicide layer formed of TiSi.sub.2, CoSi.sub.2 or NiSi.sub.2, etc. are generally used.
FIG. 1B illustrates another example of the conventional semiconductor device. Namely, the structure of the semiconductor device of FIG. 1B is the same as in FIG. 1A, except that the gate electrode 3 includes a polysilicon layer pattern 3a, a dopant diffusion barrier layer 3c and a metallic film pattern 3b. The dopant diffusion barrier layer 3c is formed of three components containing TiN or WNx, or TiN or WNx itself . The dopant diffusion barrier layer is hereinafter called as a barrier layer.
FIG. 1C illustrates yet another example of the conventional semiconductor device which includes a single metallic layer 3 as a gate electrode.
However, the above-described known semiconductor devices have the following problems.
In the above-described semiconductor devices, as shown in FIG. 1A and 1B, when the gate electrode 3 has the multilayer film structure in which the polysilicon layer 3a is deposited on the gate oxide film 2 and the metallic film pattern 3b is formed thereon, the threshold voltage Vt of the semiconductor device is determined based on the work function of the polysilicon and the doping concentration of the channel region, the metallic film pattern decreasing the resistance of the gate electrode.
However, in such semiconductor devices having the gate electrode which is the same as above, when the doping of the polysilicon layer is not sufficiently achieved, as the size of the semiconductor device and the power supply voltage decrease, a depletion layer is formed adjacent to the interface between the polysilicon and the gate insulation film, which results in deterioration of the current driving force of the semiconductor device, for example increase in Vt, in condition that the surface of the semiconductor substrate is in an inversion mode, namely, when a channel is formed.
In addition, in the polysilicon layer gate electrode, since the gate electrode of the n-channel transistor must be doped with the n-type impurity while the gate electrode of the p-channel transistor must be doped with the p-type impurity, the gate electrodes of the n-channel transistor and the p-channel transistor should be separately fabricated.
In addition, another problem may occur when using only the metallic film as the gate electrode. Specifically, the stress applied to the gate oxide film in which metallic layers of the gate electrode have different thermal expansion coefficients from each other is higher than the stress applied to the polysilicon during the heat treatment process which is performed by a predetermined number during the semiconductor fabrication, which results in decrease in the breakdown voltage, and deterioration of properties of the gate oxide film such as leakage current from the gate electrode.
Furthermore, during the etching process for forming a metallic gate electrode, the gate oxide film may be damaged, thereby degrading the characteristics of the semiconductor device.
Thus, when using the polysilicon layer as the gate electrode, the gate depletion occurs, and also when using the metallic film as the gate electrode, the characteristic of the semiconductor device are degraded due to the short channel effect and the damage of the gate oxide film.